1. Field of the Invention
The present general inventive concept relates to semiconductor memory devices. More particularly, the present general inventive concept relates to a multipath accessible semiconductor memory device having mailbox areas and a mailbox access control method thereof.
2. Description of the Related Art
In general, a semiconductor memory device having a plurality of access ports is called a multiport memory, and in particular a memory device having two access ports is called a dual-port memory. A typical dual-port memory is well-known in the field, as an image processing video memory having a RAM port accessible in a random sequence and a SAM port accessible only in a serial sequence.
Alternatively, a dynamic random access memory to read from or write to a shared memory area through a plurality of access ports in a memory cell array that does not have an SAM port, but is constructed of a DRAM cell, is called herein a multipath accessible semiconductor memory device in the present general inventive concept.
In recent portable electronic systems such as a handheld multimedia player or handheld phone, or in electronic instruments such as PDA etc., manufacturers have produced products of multiprocessor systems employing plural processors as illustrated in FIG. 1 in order to get a high speed and smooth operation.
Referring to FIG. 1, a first processor 10 and a second processor 12 are connected with each other through a connection line L10. Further, a NOR memory 14 and a DRAM 16 are coupled with the first processor 10 through determined buses B1-B3. A DRAM 18 and a NAND memory 20 are coupled with the second processor 12 through determined buses B4-B6. The first processor 10 may have a MODEM function of performing a modulation and demodulation of a communication signal. The second processor 12 may have an application function of dealing with communication data or games or performing amusements, etc. A NOR memory 14 having a NOR structure of a cell array, and a NAND memory 20 having a NAND structure of a cell array, are both nonvolatile memories having a transistor memory cell that has a floating gate. Such NOR memory and NAND memory are adapted to store data that must not be removed even if power is turned off, for example, peculiar codes of handheld instruments and data to be retained. The DRAMs 16 and 18 function as main memories for a data processing of processors.
However, in a multi processor system as illustrated in FIG. 1, DRAMs respectively correspond to and are each assigned to every processor, and UART, SPI, SRAM interfaces having a relatively low speed are used herein. Thus it is difficult to ensure a satisfactory data transmission speed, causing a complication in the size and increasing expenses for the configuration of memories. For that, a scheme illustrated in FIG. 2 is provided in order to reduce the size and to increase a data transmission speed and reduce the number of DRAMs.
In FIG. 2 one DRAM 17 is coupled with first and second processors 10 and 12 through buses B1 and B2. In order that each processor 10, 12 accesses one DRAM 17 through two paths in the multi processor system as illustrated in FIG. 2, it is required to connect two ports to corresponding buses B1 and B2. However, a typical DRAM has a single port.
It is therefore difficult to apply the multiprocessor system of FIG. 2 to a typical DRAM because of the structure of memory banks or ports.
Prior art having a configuration of FIG. 3, in which a shared memory area can be accessed by a plurality of processors, is disclosed in US Publication No. US2003/0093628 invented by Matter et. al. and published on May 15, 2003.
Referring to FIG. 3 illustrating a multiprocessor system 50, a memory array 35 is comprised of first, second and third portions. Further, the first portion 33 of the memory array 35 is accessed only by a first processor 70 through a port 37. The second portion 31 is accessed only by a second processor 80 through a port 38. The third portion 32 is accessed by all of the first and second processors 70 and 80. The size of the first and second portions 33 and 31 of the memory array 35 may be flexibly changed depending upon an operating load of the first and second processors 70 and 80. The type of the memory array 35 may be realized in a memory type or disk storage type.
To realize the third portion 32 shared by the first and second processors 70 and 80 within the memory array 35 in a structure of DRAM, memory areas of the memory array 35 and input/output sense amplifiers may be disposed and a read/write path for the respective ports may be appropriately controlled.
Furthermore, a UART, SPI, or SRAM interface has been used to get the communication between conventional processors, i.e., MODEM and application processor (or, multimedia coprocessor). Such interfaces cause a limitation in speed, an increase in the number of pins, etc. In particular, to obtain a smooth operation in three dimensional games or image communication, HDPDA, WIBRO etc., data traffic between MODEM and processors should be increased, thus the necessity in a high speed interface between processors tends to increase.
An adequate solution capable of sharing a shared memory area allocated in a DRAM memory cell array and simultaneously solving a problem caused by a low-speed interface outside a memory, in a multiprocessor system having two or more processors is needed. This is described with reference to FIG. 4.
FIG. 4 is a block diagram illustrating a multiprocessor system having a conventional multipath accessible semiconductor memory device (DRAM). With reference to FIG. 4, a portable communication system includes a first processor 10, a second processor 12, and a DRAM 17 that includes memory areas accessed by the first and second processors 10 and 20 within a memory cell array. The portable communication system also includes flash memories 101 (NOR) and 102 (NAND/OneNAND) connected to the first and second processors 10 and 12 through each bus.
Though not limited, the DRAM 17 illustrated in FIG. 4 may be configured to have two independent ports. If a port A having an output of signal INTa is herein called a first port and a port B having an output of signal INTb is called a second port, the first port is connected to the first processor 10 through a general-purpose input/output (GPIO) line, and the second port is connected to the second processor 12 through a general-purpose input/output (GPIO) line. The first processor 10 may have a MODEM function of performing a modulation and demodulation of a communication signal, a baseband processing function, etc. The second processor 12 may have an application function to process communication data or perform game, moving image, amusement, etc. The second processor 12 may be a multimedia coprocessor if necessary.
The flash memories 101 and 102 are nonvolatile memories constructed of one or more MOS transistors, in which the cell connected configuration of a memory cell array has a NOR or NAND structure and a memory cell has a floating gate. The flash memories 101 and 102 are adapted to store data that is not removed even if power is turned off, for example, peculiar codes of handheld instruments and data to be retained.
As illustrated in FIG. 4, the DRAM 17 having a dual port may be used to store commands and data to be executed by the processors 10 and 12. Further, the DRAM 17 is in charge of an interface function between the first and second processors 10 and 12. In a communication between the first and second processors 10 and 12, a DRAM interface is used instead of an external interface. To provide an interface between processors through DRAM, an interface unit such as a register, buffer, etc. is adapted inside the DRAM. The interface unit has a semaphore area and mailbox areas that may be a familiar concept to processing system developers. A specific row address, i.e., 1FFF800h˜1FFFFFFh, 2 KB size=1 row size, of enabling an optional one row of a shared memory area in DRAM, is changeably allocated to an internal register as the interface unit. That is, when the specific row address 1FFF800h˜1FFFFFFh is applied, a specific word line corresponding to the shared memory area is disabled, and the interface unit is enabled.
As a result, systematically, the semaphore area and the mailbox areas of the interface unit are accessed by using a direct address mapping method, and internally in a DRAM, a command accessed with a corresponding disabled address is decoded and the mapping is performed with the register adapted inside the DRAM. Thus, for this area, a memory controller of a chip set generates a command in the same method as a cell of other memory.
The mailbox areas are specifically adapted each per port (per processor). In a dual-port, two sorts are provided. In the mailbox areas, a mailbox A to B area is writable in a first processor 10, but only readable and a write operation is not allowed in second processor 12. To the contrary, a mailbox B to A area is writable in a second processor 12, but only readable and the write operation is not allowed in first processor 10.
The mailbox A to B may be called herein a first mailbox and the mailbox B to A may be called herein a second mailbox. The first mailbox may be provided to transmit a message through the first port, or from the first processor 10 to the second processor 12 or second port. The second mailbox may be provided to transmit a message through the second port or from the second processor 12 to the first processor 10 or first port.
A control right to shared memory area is represented in the semaphore area allocated to the register, and a message, i.e., a request for the right, data transfer, command transmission, etc., given to a counterpart processor is written to the mailbox area in a predetermined transmission direction. Particularly, in transferring a message to a counterpart processor through a mailbox area, a mailbox write command is used. When the write command is produced, the DRAM generates interrupt signals INTa and INTb as an output signal to execute an interrupt processing service of a corresponding processor in a predetermined direction, and this output signal is coupled to a GPIO of a corresponding processor, or UART, etc., in hardware. The interrupt signals INTa and INTb function as the signal of informing the counterpart processor of having written a message to the mailbox area.
As the necessity for semiconductor memory devices (DRAM) having a mailbox area for communication of a message such as an access right request, data transfer, command transmission, etc., as described above, increases, it is also required to efficiently dispose the mailboxes so as to substantially reduce the increase of chip size and to efficiently configure a message access path to provide access to the mailbox.